Integrated Design, Verification and Reuse for FPGA design flows

Overview: FPGA Seminar at Technology Park Ljubljana.

WEDASoft and Technology Park Ljubljana are inviting you to attend an international seminar on Mentor Graphics' design flow for FPGA (and ASIC) designers.

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***** This presentation will include an overview of Mentor Graphics' design flow for FPGA (and ASIC) designers. This will show the enabling technologies that Mentor provides to enable companies and research establisments to more rapidly and effectively create and verify designs which incorporate a mix of new and existing RTL. The key areas this will cover include the following:

Accelerating RTL Reuse
Automatic RTL Code Quality Assessment
Requirements Tracking
Using Assertion Monitors for automatic functional checks

The Lecturer: Neil Rattray

Neil holds a B.Eng in Electronic Engineering from Queen Mary College, University of London, and has over 20 years experience in ASIC and FPGA design. He worked initially for 8 years for several defence companies in the UK. From there, he went into applications engineering for first Actel and then Xilinx distributors where he supported many customers across the UK and Ireland. He then worked for 7 years for Saros Technology supporting numerous EDA vendors, including Mentor. For the past 18 months Neil has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects across europe.

What you will learn

Accelerating RTL Reuse

Here we will demonstrate the powerful RTL capture and visualization capabilities of the Mentor Graphics FPGA Design flow. Design intent is automatically captured using a graphical method, which includes

Block Diagram
State Machine (Finite and Algorithmic)
Flow Chart
Truth Table

This graphical technique makes the understanding of the design intent more simple for reviewing and making any modifications to existing designs.

Graphical capture and visualization gives an automatic documentation of the design which will always be up to date, which can be used for reviewing the design.

Automatic RTL Code Quality Assessment

Assessing the quality of RTL code can be a subjective matter - RTL code written by one engineer can potentially be unreadable by anither unless good coding practices are followed. This can be as complex as specifying the data types and packages used or as simple as specifying that signal names are capilatized.

Defining your companies coding standards in a tool wich can then automate the checking flow means that all the code produced follows the internal rules and thus ensures that any code produced can be more easily understood by design and verification engineers alike.

Requirements Tracking

Specifications of design and verification intent are normally produced from a single requirements specification, however the tracking of how complete these have been implemented and verified are often subjective. The question of "when are we completed verifying?" is often impossible to quantify precisely, but is most frequently the result of a "best estimate" by an experienced project engineer or manager.

By automating this tracking we can quantify the implementation of amongst others, the design coding, the testbench coding, the testbench coverage. These are important measures of timescales by engineering and project management.

The impact of late changes to design or requirements can also be accuratey estimated for both timescales and costing purposes.

Using Assertion Monitors for automatic functional checks

Assertions allow both designer engineers and verification engineers to concisely describe the intended and required functionality of RTL code. By attaching these assertions to the RTL code we provide automatic functional checks of this code which make it both easier to detect functional problems within the design and more precisely locate these problems. The automated detection allows a larger set of test vectors to be easily applied to the design whilst the detection of problems points the design or verification engineer to the precise blocks where any problems originate and hence speed up the location and resolution of these issues.

PSL and SystemVerilog Assertions (SVA) are standard languages to describe these monitors and either of these can be used to describe this intended and required functionality.